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S25FL016A0LMAI011 Datasheet(PDF) 21 Page - SPANSION |
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S25FL016A0LMAI011 Datasheet(HTML) 21 Page - SPANSION |
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21 / 34 page ![]() August 28, 2006 S25FL016A_00_C0 S25FL016A 19 Da ta Shee t (Prelim i nar y ) Figure 9.8 Page Program (PP) Command Sequence 9.9 Sector Erase (SE) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any address within the sector (see Table 7.1 on page 11) is a valid address for the SE command. CS# must be driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.9 and Table 9.4. The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise the device does not execute the command. The SE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tSE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute an SE command that specifies a sector that is protected by the Block Protect bits (BP2:BP0) (see Table 7.1 on page 11). Figure 9.9 Sector Erase (SE) Command Sequence 0 34 33 32 31 30 29 28 10 9 8 7 6 5 4 3 2 1 35 36 37 38 39 46 45 44 43 42 41 40 47 48 49 50 51 52 53 54 55 23 22 21 3 21 07 6 5 4 3 2 1 0 Data Byte 1 24-Bit Address Command Data Byte 2 Data Byte 3 Data Byte 256 MSB MSB MSB MSB MSB SCK SI SCK SI 7 65 4 3 2 1 0 76 54 3 21 0 7 6 5 4 3 21 0 CS# CS# Mode 0 Mode 3 CS# SCK SI SO MSB Command 24-bit Address 01 2 3 45 6 7 8 910 28 29 30 31 23 22 21 3 2 1 0 Hi-Z Mode 0 Mode 3 |
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