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STM32L151CBT7ADTR Datasheet(PDF) 57 Page - STMicroelectronics

Part # STM32L151CBT7ADTR
Description  Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3,128KB Flash, 32KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC
PDF  130 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L151CBT7ADTR Datasheet(HTML) 57 Page - STMicroelectronics

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STM32L151x6/8/B-A STM32L152x6/8/B-A
Electrical characteristics
105
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in the following table.
PD
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix 7(4)
UFBGA100 package
-
339
mW
LQFP100 package
-
435
TFBGA64 package
-
308
LQFP64 package
-
444
LQFP48 package
-
364
UFQFPN48 package
-
606
TA
Ambient temperature for 6 suffix version Maximum power dissipation(5)
–40
85
°C
Ambient temperature for 7 suffix version Maximum power dissipation
–40
105
TJ
Junction temperature range
6 suffix version
–40
105
°C
Junction temperature range
7 suffix version
–40
110
1. When the ADC is used, refer to Table 55: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and operation.
3. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 13: Thermal characteristics on
page 56).
5. In low-power dissipation state, TA can be extended to -40°C to 105°C temperature range as long as TJ does not exceed TJ
max (see Table 13: Thermal characteristics on page 56).
Table 14. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Table 15. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tVDD(1)
VDD rise time rate
BOR detector enabled
0
-
∞
µs/V
BOR detector disabled
0
-
1000
VDD fall time rate
BOR detector enabled
20
-
∞
BOR detector disabled
0
-
1000
TRSTTEMPO(1) Reset temporization
VDD rising, BOR enabled
-
2
3.3
ms
VDD rising, BOR disabled(2)
0.4
0.7
1.6
VPOR/PDR
Power on/power down reset
threshold
Falling edge
1
1.5
1.65
V
Rising edge
1.3
1.5
1.65



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