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STM32L151CBT7ADTR Datasheet(PDF) 129 Page - STMicroelectronics |
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STM32L151CBT7ADTR Datasheet(HTML) 129 Page - STMicroelectronics |
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129 / 130 page ![]() DocID024330 Rev 5 129/130 STM32L151x6/8/B-A STM32L152x6/8/B-A Revision history 129 25-Aug-2017 5 Updated Table 43: I/O static characteristics pull-up and pull-down values. Updated Table 46: NRST pin characteristics pull-up values. Updated Section 7: Package information adding information about other optional marking or inset/upset marks. Updated note 1 below all the package device marking figures. Updated Nested vectored interrupt controller (NVIC) in Section 3.2: ARM® Cortex®-M3 core with MPU about process state automatically saved. Updated Table 3: Functionalities depending on the operating power supply range removing I/O operation column and adding note about GPIO speed. Updated Table 42: I/O current injection susceptibility note by ‘injection is not possible’. Updated Figure 20: Recommended NRST pin protection note about the 0.1uF capacitor. Updated Section 3.1: Low-power modes Low-power run mode (MSI) RC oscillator clock. Updated Table 5: Working mode-dependent functionalities (from Run/active down to standby) disabling I2C functionality in Low- power Run and Low-power Sleep modes. Table 74. Document revision history (continued) Date Revision Changes |
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