ICS844251BGI-14 REVISION A June 6, 2016

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©2016 Integrated Device Technology, Inc.

ICS844251I-14 Data Sheet

FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS844251I-14 provides

separate power supplies to isolate any high switching noise from the

outputs to the internal PLL. VDD and VDDA should be individually

connected to the power supply plane through vias, and 0.01µF

bypass capacitors should be used for each pin. Figure 3 illustrates

this for a generic VDD pin and also shows that VDDA requires that an

additional 10

 resistor along with a 10F bypass capacitor be

connected to the VDDA pin.

Figure 3. Power Supply Filtering

2.5V LVDS Driver Termination

Figure 4 shows a typical termination for LVDS driver in characteristic

impedance of 100

 differential (50 single) transmission line

environment. For buffer with multiple LVDS driver, it is recommended

to terminate the unused outputs.

Figure 4. Typical LVDS Driver Termination

VDD

VDDA

2.5V

10

Ω

10µF

.01µF

.01µF

2.5V

LVDS Driver

R1

100

Ω

–

+

2.5V

50

Ω

50

Ω

100

Ω Differential Transmission Line