COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

13

Figure 4. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially

Figure 6. FIFO Read Cycle Timing

NOTE:

1. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.

Figure 5. FIFO Write Cycle Timing

CLKA

RST

IR

FS1/

SEN

FS0/SD

4

AF Offset

(Y) MSB

AE Offset

(X) LSB

3023 drw07

tFSS

tFSS

tFSH

tSPH

tSENS

tSENH

tSDS

tSDH

tSENS

tSENH

tSDS

tSDH

tPIR

CLKA

IR

ENA

MBA

CSA

W/

RA

tCLKH

tCLKL

tCLK

tENS2

tENS2

tENS2

tENS1

tENH2

tENH2

tENH2

tENH1

tENS1

tENH1

tENH1

tENS1

3023 drw08

A0 - A35

tDS

tDH

W1

W2

No Operation

HIGH

3023 drw09

CLKB

OR

ENB

B0 - B35

MBB

CSB

W/RB

tCLK

tCLKH

tCLKL

tENS1

tA

tMDV

tEN

tA

tENS1

tENH1

tENS1

tENH1

W1

W2

W3

tENH1

tDIS

No Operation

HIGH