14

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

Figure 7. OR Flag Timing and First Data Word Fall Through when the FIFO is Empty

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB

cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and the first word load to the output register may

occur one CLKB cycle later than shown.

CSA

W/

RA

MBA

IR

A0 - A35

CLKB

OR

CSB

W/RB

MBB

ENA

ENB

B0 -B35

CLKA

12

3

3023 drw10

tCLKH

tCLKL

tCLK

tENS2

tENS1

tENH2

tENH1

tDS

tDH

tSKEW1

tCLK

tCLKL

tPOR

tPOR

tENS1

tENH1

tA

Old Data in FIFO Output Register

W1

FIFO Empty

LOW

HIGH

LOW

HIGH

LOW

tCLKH

W1

HIGH

(1)