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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

Figure 10 Write protocol with 7-bit Slave Address (ADS=0).

I2C writes to memory align on 32-bit word boundaries, thus the 24 address MSBs must be provided while the 2 LSB’s associated with word and byte

pointers are DON’T CARE and are therefore not transmitted.

Figure 11 Read protocol with 7-bit Slave Address (ADS=0)

CPS-10Q Configuration and Image (Master mode)

There is both a power up master and a command master mode. If powered up in master mode, the CPS-10Q polls configuration image from external

memory after the device reset sequence has completed. Once the device has completed its configuration sequence, it will revert to slave mode.

Through a config register write, the device can be commanded to enter master mode, which provides more configuration sequence flexibility. Refer to

“CPS-10Q User Manual” for details.

Memory

Address [23:18]

Memory

Address [17:10]

Memory

Address [9:2]

45

54

63

27

36

73

18

SLAVE ADDR

A

0

0

S

9

R=1 | W=0

Device

Address [6:0]

DATA

A

A

DATA

DATA

A

DATA

A

A

DATA

DATA

A

DATA

_

A

P

Input Data

[31:24]

Input Data

[23:16]

Input Data

[15:8]

Input Data

[7:0]

A

46

55

64

73

83

Memory

Address [23:18]

Memory

Address [17:10]

Memory

Address [9:2]

27

36

18

SLAVE ADDR

A

0

0

S

9

R=1 | W=0

Device

Address [6:0]

DATA

A

A

DATA

DATA

A

DATA

A

A

DATA

DATA

A

DATA

_

A

P

_

A

Output Data

[31:24]

Output Data

[23:16]

Output Data

[15:8]

Output Data

[7:0]

Sr SLAVE ADDR

A

1

R=1 | W=0

Device

Address [6:0]