DAC1408D750 datasheet(21/96 Pages) RENESAS

Part #	DAC1408D750

Description	Dual 14-bit DAC; up to 750 Msps; 2, 4 or 8 interpolating with JESD204A interface

PDF	96 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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21 / 96 page

DAC1408D750 4

Product data sheet

Rev. 04 — 2 July 2012

21 of 96

Integrated Device Technology

DAC1408D750

, 4 or 8 interpolating DAC with JESD204A

10.2.6 Frame assembly

DAC1408D750 supports only /F/ = 1, which means that every frame clock period carries

one byte per lane. Frame assembly combines the octet of lane_0 with the six MSB bits of

lane_1 and reassembles the original 14-bit sample. The same is done for lane_2 and

lane_3. Tail bits are dropped.

The frame assembler also handles previously triggered errors.

If scrambling is enabled:

If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in

lane_0 and/or lane_1, the previous 14-bit sample is repeated twice for I (lane_0,

lane_1). The same is done for Q (lane_2, lane_3).

If scrambling is disabled:

If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in

lane_0 and/or lane_1, the previous 14-bit sample is repeated once for I (lane_0,

lane_1). The same is done for Q (lane_2, lane_3).

DAC1408D750 Datasheet(PDF) 21 Page - Renesas Technology Corp