4

AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)

SYMBOL

PARAMETER

LIMITS

UNITS

TEST

CONDITIONS

HM-6516B-9

HM-6516-9

MIN

MAX

MIN

MAX

(1) TELQV

Chip Enable Access Time

-

120

-

200

ns

(Notes 1, 3)

(2) TAVQV

Address Access Time

-

120

-

200

ns

(Notes 1, 3, 4)

(3) TELQX

Chip Enable Output Enable Time

10

-

10

-

ns

(Notes 2, 3)

(4) TWLQZ

Write Enable Output Disable Time

-

50

-

80

ns

(Notes 2, 3)

(5) TEHQZ

Chip Enable Output Disable Time

-

50

-

80

ns

(Notes 2, 3)

(6) TGLQV

Output Enable Output Valid Time

-

80

-

80

ns

(Notes 1, 3)

(7) TGLQX

Output Enable Output Enable Time

10

-

10

-

ns

(Notes 2, 3)

(8) TGHQZ

Output Enable Output DisableTime

-

50

-

80

ns

(Notes 2, 3)

(9) TELEH

Chip Enable Pulse Negative Width

120

-

200

-

ns

(Notes 1, 3)

(10) TEHEL

Chip Enable Pulse Positive Width

50

-

80

-

ns

(Notes 1, 3)

(11) TAVEL

Address Setup Time

0

-

0

-

ns

(Notes 1, 3)

(12) TELAX

Address Hold Time

30

-

50

-

ns

(Notes 1, 3)

(13) TWLWH

Write Enable Pulse Width

120

-

200

-

ns

(Notes 1, 3)

(14) TWLEH

Write Enable Pulse Setup Time

120

-

200

-

ns

(Notes 1, 3)

(15) TELWH

Write Enable Pulse Hold Time

120

-

200

-

ns

(Notes 1, 3)

(16) TDVWH

Data Setup Time

50

-

80

-

ns

(Notes 1, 3)

(17) TWHDX

Data Hold Time

10

-

10

-

ns

(Notes 1, 3)

(18) TELEL

Read or Write Cycle Time

170

-

280

-

ns

(Notes 1, 3)

NOTES:

1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:

1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

2. Tested at initial design and after major design changes.

3. VCC = 4.5V and 5.5V.

4. TAVQV = TELQV + TAVEL.

HM-6516