P25Q64U datasheet(21/97 Pages) PUYA

21 / 97 page

P25Q64U Datasheet

Puya Semiconductor

Page 21 of 97

Hold Feature

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop

the operation of write status register, programming, or erasing in progress.

The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal

while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not

start until Serial Clock signal being low).

The HOLD condition ends on the rising edge of HOLD# pin signal

while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not

end until Serial Clock being low).

Figure 9-1 Hold Condition Operation

HOLD

CS#

SCLK

HOLD#

During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will

keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock

(SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip

Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start

communication with chip, the HOLD# must be at high and CS# must be at low.

Note: The HOLD feature is disabled during Quad I/O mode.

P25Q64U Datasheet(PDF) 21 Page - Puya Semiconductor Co., Ltd.