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NB4L16M Datasheet(PDF) 5 Page - ON Semiconductor |
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NB4L16M Datasheet(HTML) 5 Page - ON Semiconductor |
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5 / 12 page ![]() NB4L16M http://onsemi.com 5 Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V, VEE = 0 V; (Note 8) Symbol Characteristic −40°C 25°C 85°C Unit Min Typ Max Min Typ Max Min Typ Max VOUTPP Output Voltage Amplitude (@VINPPmin)fin ≤ 3.5 GHz (Figures 3 and 4) fin ≤ 4.5 GHz 280 150 400 300 280 150 400 300 280 150 400 300 mV fDATA Maximum Operating Data Rate 3.5 5.0 3.5 5.0 3.5 5.0 Gb/s tPLH, tPHL Propagation Delay to Output Differential @ 0.5 GHz (Figure 6) 175 215 265 175 220 265 175 225 265 ps tSKEW Duty Cycle Skew (Note 9) Device−to−Device Skew (Note 13) 2.0 6.0 10 90 2.0 6.0 10 90 2.0 6.0 10 90 ps tJITTER RMS Random Clock Jitter (Note 11) fin ≤ 4.5 GHz Peak−to−Peak Data Dependent Jitter (Note 12) fDATA = 2.5 Gb/s fDATA = 3.5 Gb/s fDATA = 5.0 Gb/s 0.2 1.5 2.0 9.0 0.7 10 12 25 0.2 1.5 2.0 9.0 0.7 10 12 25 0.2 1.5 2.0 9.0 0.7 10 12 25 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) 75 VCC −VEE 75 VCC −VEE 75 VCC −VEE mV tr tf Output Rise/Fall Times @ 0.5 GHz (Figure 5) (20% − 80%) 60 90 60 90 60 90 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). See Figure 12 and 14. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz. 10.VINPP(MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode. See Figure 11. 11. Additive RMS jitter with 50% duty cycle input clock signal. 12.Additive peak−to−peak data dependent jitter with NRZ input data signal, PRBS 223−1 and K28.7 pattern. See Figures 7, 8, 9, 10, 11 and 12. 13.Device−to−device skew is measured between outputs under identical transition @ 0.5 GHz. |
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