ADC08B3000 datasheet(21/32 Pages) NSC

21 / 32 page

1.0 Functional Description (Continued)

TABLE 3. Register Addresses

4-Bit Address

Loading Sequence:

A3 loaded after H0, A0 loaded last

Hex

Reserved

Configuration

Offset

Full-Scale Voltage

Adjust

Reserved

Extended Clock

Phase Adjust Fine

Extended Clock

Phase Adjust

Coarse

FIFO

1.4 REGISTER DESCRIPTION

Eight write-only registers provide several control and con-

figuration options in the Extended Control Mode. These reg-

isters have no effect when the device is in the Normal

Control Mode. Each register description below also shows

the Power-On Reset (POR) state of each control bit.

Configuration Register

Addr: 1h (0001b)

W only (0xBEFF)

D15

D14

D13

D12

D11

D10

DCS

DCP

nDE

111111

Bit 15

Must be set to 1b

Bit 14

Must be set to 0b

Bit 13

Must be set to 1b

Bit 12

DCS: Duty Cycle Stabilizer. When this bit is

set to 1b , a duty cycle stabilzation circuit is

applied to the clock input. When this bit is set

to 0b the stabilzation circuit is disabled.

POR State: 1b

Bit 11

DCP: DDR Clock Phase. This bit only has an

effect in the DDR mode. When this bit is set

to 0b, the DRDY edges are time-aligned with

the data bus edges (“0˚ Phase”). When this

bit is set to 1b, the DRDY edges are placed

in the middle of the data bit-cells (“90˚

Phase”).

POR State: 1b

Bit 10

nDE: DDR Enable. When this bit is set to 0b,

data bus clocking follows the DDR (Dual

Data Rate) mode whereby a data word is

output with each rising and falling edge of

DRDY. When this bit is set to a 1b, data bus

clocking follows the SDR (Single Data Rate)

mode whereby each data word is output with

either the rising or falling edge of DRDY, as

determined by the OutEdge bit.

POR State: 1b

Bit 9

Must be set to 1b

Bit 8

OE: Output Edge. This bit selects the edge of

the DRDY pins with which the data words

transition in the SDR mode and has the

same effect as the OutEdge pin in the normal

control mode. When this bit is set to 1b, the

data outputs change with the rising edge of

the DRDY pins. When this bit is set to 0b, the

data outputs change with the falling edge of

the DRDY pins.

POR State: 0b

Bits 7:6

Must be set to 1b.

Bits 5:0

Must be set to 1b

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