PCA9516AD datasheet(6/13 Pages) PHILIPS

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Philips Semiconductors

Product data sheet

PCA9516A

5-channel I2C hub

2004 Sep 29

In order to illustrate what would be seen in a typical application,

refer to Figures 5 and 6. If the bus master in Figure 4 were to write

to the slave through the PCA9516A, we would see the waveform

shown in Figure 5 on Bus 0. This looks like a normal I2C

transmission until the falling edge of the 8th clock pulse. At that

point, the master releases the data line (SDA) while the slave pulls it

LOW through the PCA9516A. Because the VOL of the PCA9516A is

typically around 0.5 V, a step in the SDA will be seen. After the

master has transmitted the 9th clock pulse, the slave releases the

data line.

On the Bus 1 side of the PCA9516A, the clock and data lines would

have a positive offset from ground equal to the VOL of the

PCA9516A. After the 8th clock pulse, the data line will be pulled to

the VOL of the slave device that is very close to ground in our

example.

It is important to note that any arbitration or clock stretching events

on Bus 1 require that the VOL of the devices on Bus 1 be 70 mV

below the VOL of the PCA9516A (see VOL – Vilc in the DC

Characteristics section) to be recognized by the PCA9516A and

then transmitted to Bus 0.

9th CLOCK PULSE

VOL OF MASTER

VOL OF PCA9516A

2 V/DIV

SW02250

Figure 5. Bus 0 waveform

9th CLOCK PULSE

VOL OF SLAVE

VOL OF PCA9516A

2 V/DIV

SW02251

Figure 6. Bus 1 waveform

PCA9516AD Datasheet(PDF) 6 Page - NXP Semiconductors