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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 51

�� = 4 × 2 × 308 = 2464 ��

Figure 74:

Complete 8-Bit Timing Clocks with ROI On for Readout Mode 1-To-1

Parameters

Clocks

RST_CDS

100

ADC Time

280

Readout Data

308

Readout Time

334

SAMPLE

START_AD

TBTW_START_AD&RST_RAMP

TBTW_SAMPLE&START_AD

FCT

335

MTA => Line Rate

335 => 238.8 kHz

DTI

112

Max Integration Time

223 => 2787.5 ns

Minimum LVALLow_Period

��_�� = 335 − 308 = 27 ��

The minimum LVAL time at low between two consecutive data streams is 27 clocks.

For 2-To-1 and 4-To-1 modes, if the goal is still achieve the maximum line rate, the ROI needs to

decreased even more, because the number of the output is also lower. Please note that the minimum

LVAL low period needs always to be in consideration.

For 2-To-1 mode:

●

Start Region of Interest Register Segment A = 0x7B = 123d

●

Start Region of Interest Register Segment B = 0x00

●

End Region of interest Register Segment A = 0xA0 = 160d

●

End Region of Interest Register Segment B = 0x25 = 37d

�� = ((160 − 123) + 1) × (4 × 2)) = 304 ��

�� = 304 + 30 = 334 ��

�� = 2 × 2 × 304 = 1216 ��

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