CDB4923 datasheet(13/50 Pages) CIRRUS

13 / 50 page

CDB4923 CDB49300

DS262DB2

As mentioned above, many of the PLD’s I/O pins

are tri-stated. The complete list of tri-stated pins

for full external mode (PLD Mode 0) can be found

in Table 6. The complete list of tri-stated pins for

external control mode (PLD Mode 1) can be found

in Table 7.

By design, the clocking signals present at the

MCLK,

LRCLK,

and

SCLK

pins

the

CS492x/CS493xx are used to drive both the audio

input and output circuitry for the rest of the

CDB4923/300 as shown in Figure 3. This means

that the S/PDIF input, S/PDIF output, analog out-

put and analog input continue to function in the

EXTERNAL modes. The user should only drive

audio clocks in PLD Mode 0. PLD Mode 1 derives

audio clocks from the CS8414.

The three clocking configurations that the user

should be aware of when using PLD Mode 0 are:

•

DSP is slave to all audio clocks - user drives

MCLK/SCLK/LRCLK

•

DSP masters LRCLK/SCLK - user drives

MCLK

•

DSP masters MCLK/LRCLK/SCLK - user

drives no audio clocks

Only when the correct clocking is present on the

23MCLK, 23LRCLK, and 23SCLK pins (J12),

processed audio can be heard on the analog outputs

(J13 - J20) and the digital outputs (J45 - J47). The

analog outputs J13-J20 can be found in Figure 12,

and the digital outputs can be found in Figure 13.

The information in Table 9 summarizes the opera-

tion of switch S3. The table shows the data routing

configuration, the MCLK source, and the method

of board control. This is intended as a quick refer-

ence and can also be found in Appendix J: Switch

Summary.

Pin Name

Number

Pin Name

Number

MCLK

DATA0

CMPCLK

DATA1

CMPREQ

DATA2

CMPDAT

DATA3

SCLKN1

DATA4

SLRCLKN1

DATA5

SDATAN1

DATA6

RESET

DATA7

A1, CDIN

A0, SCCLK

EXTMEM

SCPDIO

Table 6. DSP Pins Tri-Stated by U11 in PLD Mode 0

Pin Name

Number

Pin Name

Number

RESET

DATA0

DATA1

DATA2

A1, CDIN

DATA3

A0, SCCLK

DATA4

SCPDIO

DATA5

DATA6

DATA7

Table 7. DSP Pins Tri-Stated by U11 in PLD Mode 1

MCLK

Source

Description

J12

The user must provide an oversampling clock on

the 23MCLK pin of stake header J12. (NOTE:

This clock signal must be +3.3 V logic when

using CS493xx)

CS8414 The CS8414 (U13) derives the sampling fre-

quency (Fs) from an incoming S/PDIF stream

and masters a 256 Fs MCLK

DSP

The DSP (U1) masters MCLK, generally when

using broadcast application code

Table 8. Clocking Descriptions

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