TMPR4925 datasheet(198/590 Pages) TOSHIBA

198 / 590 page

Chapter 8 DMA Controller

8-28

8.4.3

DMA Channel Status Register (DMCSRn)

0xB01C (ch. 0)

0xB03C (ch. 1)

0xB05C (ch. 2)

0xB07C (ch. 3)

WAITC

: Type

0x0000

: Initial value

7654

3210

Reserved

CHNEN STLXFER XFACT ABCHC NCHNC NTRNFC EXTDN CFERR CHERR DESERR SORERR

R/W1C

R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type

0000

: Initial value

Bits

Mnemonic

Field Name

Description

31:16

WAITC

Wait Counter

Wait Counter (Initial value: 0x0000, R)

This is a diagnostic function.

I/O DMA transfer mode (DMCCRn.EXTRQ = “1”)

This counter is decremented by 1 at each 64 G-Bus cycles. After channel n releases

bus ownership, this counter sets the default (the value that is the detection interval

clock cycle count set by the Transfer Stall Detection Interval field

(DMCCRn.STLTIME) divided by 64). The Transfer Stall Detect bit

(DMCSRn.STLXFER) is set when the interval during which bus ownership is not held

reaches the set clock cycle. The counter is reset to the default and stops counting.

Clearing the Transfer Stall Detect bit (DMCSRn.STLXFER) resumes the count and

starts stall detection.

Memory transfer mode (DMCCRn.EXTRQ = “0”)

This counter is decremented by 1 at each G-Bus cycle. After bus ownership is

released, the counter is set to the delay clock cycle count set by the Internal Request

Delay field (DMCCRn.INTRQD). When the counter reaches “0” the count stops and

channel n requests bus ownership.

15:11



Reserved



CHNEN

Chain Enable

Chain Enable (Initial value: 0, R)

This value is a copy of the Chain Enable bit (CHNEN) of the DMA Channel Control

STLXFER

Transfer Stall

Detect

Stalled Transfer Detect (Initial value: 0, R/W1C)

This bit indicates whether the interval during which bus ownership is not held

exceeds the value set by the Transfer Stall Detect Interval field (DMCCRn.STLTIME)

after bus ownership is released when in the I/O DMA transfer mode.

1: Indicates that the interval during which bus ownership was not held exceeds the

DMCCRn.STLTIME setting.

0: The interval during which bus ownership was not held did not exceed the setting

since this bit was last cleared.

Figure 8.4.3 DMA Channel Status Register (1/2)

TMPR4925 Datasheet(PDF) 198 Page - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 198 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL