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TMPR4925 Datasheet(PDF) 200 Page - Toshiba Semiconductor

Part # TMPR4925
Description  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 200 Page - Toshiba Semiconductor

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Chapter 8 DMA Controller
8-30
8.4.4
DMA Source Address Register (DMSARn)
0xB004 (ch. 0)
0xB024 (ch. 1)
0xB044 (ch. 2)
0xB064 (ch. 3)
31
16
SADDR[31:16]
R/W
: Type
-
: Initial value
15
0
SADDR[15:0]
R/W
: Type
-
: Initial value
Bits
Mnemonic
Field Name
Description
31:0
SADDR
Source Address
Source Address (Initial value: undefined, R/W)
This field sets the physical address of the transfer source during Dual Address
transfer. This field sets the physical address of memory access during Single
Address transfer. This field is used for either Memory-to-I/O or I/O-to-Memory
transfers.
Refer to “8.3.7.1 Channel Register Settings During Single Address Transfer” and
“8.3.8.1 Channel Register Settings During Dual Address Transfer” for more
information.
During Burst transfer, the value changes once for each bus operation only by the size
that was transferred. During Single transfer, the value only changes by the value
specified by the DMA Source Address Increment Register (DMSAIRn).
Figure 8.4.4 DMA Source Address Register



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