TMPR4925 datasheet(202/590 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-32

8.4.6

DMA Chain Address Register (DMCHARn)

0xB000 (ch. 0)

0xB020 (ch. 1)

0xB040 (ch. 2)

0xB060 (ch. 3)

CHADDR[31:16]

R/W

: Type

: Initial value

CHADDR[15:3]

Reserved

R/W

: Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:2

CHADDR

Chain Address

Chain Address (Initial value: undefined, R/W)

When Chain DMA transfer is executed, this register sets the physical address of the

next DMA Command Descriptor to be read. If DMA transfer according to the current

Channel Register setting ends and the Chain Enable bit (DMCCRn.CHNEN) is set,

then the DMA Command Descriptor is loaded in the Channel Register starting from

the address indicated by this register.

When a value other than “0” is set in this register, the Chain Enable bit

(DMCCRn.CHNEN) and the Transfer Active bit (DMCCRn.XFACT) are set. When “0”

is set in this register, only the Chain Enable bit (DMCCRn.CHNEN) is cleared.

When the Chain Address field value reads a DMA Command Descriptor of 0, the

value of this register is not updated and the value before that one (address of the

Data Command Descriptor when the value of the Chain Address field being read was

“0”) is held.

2:0



Reserved



Figure 8.4.6 DMA Chain Address Register

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