CS5535 datasheet(31/555 Pages) NSC

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Signal Definitions (Continued)

2.2

SIGNAL DESCRIPTIONS

Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi-

cal information.

2.2.1

System Interface Signals

Signal Name

Ball No.

Type

Description

MHZ66_CLK

A10

66 MHz Clock. This is the main system clock. It is also used by the

IDE interface.

MHZ48_CLK

N17

USB Clock. This is the 48 MHz clock for the UARTs and SMB Con-

troller.

MHZ14_CLK

14.31818 MHz Timer Clock. This is the input clock for power man-

agement functions and the Programmable Interval Timers (PITs).

KHZ32_XCI

Wire

32 kHz Input. This input is used for the real-time clock (RTC), GPIOs,

MFGPTs, and power management functions.

This input may come from either an external oscillator or one side of a

32.768 kHz crystal. If an external oscillator is used, it should be pow-

ered by VIO_VSB. This signal takes approximately one second to lock

after power-up.

KHZ32_XCO

Wire

32 kHz Input 2. This input is to be connected to the other side of the

crystal oscillator connected to KHZ32_XCI, if used. Leave open (not

connected) if an oscillator (not a crystal) is connected to KHZ32_XCI.

RESET_WORK#

Reset Working Power Domain. This signal, when asserted, is the

master reset for all CS5535 interfaces that are in the Working power

domain. See Section 3.9 "Power Management" on page 72 for a

description of the Working power domain.

RESET_WORK# must be asserted for at least 10 ns in order to be

properly recognized.

If LVD_EN# is enabled (tied low) use of this input is not required. See

the LVD_EN# signal description for further details.

RESET_STAND#

Reset Standby Power Domain. This signal, when asserted, is the

master reset for all CS5535 interfaces that are in the Standby power

domain. See Section 3.9 "Power Management" on page 72 for a

description of the Standby power domain.

If LVD_EN# is enabled (tied low) use of this input is not required. See

the LVD_EN# discussion in this table.

Tie directly to VIO_VSB if not used.

RESET_OUT#

Reset Output. This is the main system reset signal. RESET_OUT# is

de-asserted synchronously with the low-to-high edge of PCI_CLK.

The de-assertion is delayed from internal reset by up to 32 seconds,

with an 8 ms default value, using a programmable counter driven by

the 32 kHz clock. Note this counter default is established by

RESET_STAND# and is not affected by RESET_WORK#. Therefore,

the delay value may be changed and the system reset with the new

value.

WORKING

Working State. Indicates the chip is in the Working state when high.

This signal is intended to be used to control power to off-chip devices

in a system. Open-drain. External pull-up required.

CS5535 Datasheet(PDF) 31 Page - National Semiconductor (TI)

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