CS5535 datasheet(68/555 Pages) NSC

68 / 555 page

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Revision 0.8

Global Concepts and Features (Continued)

3.8.3.1

ASMI

ASMIs fall into two classes: direct and in-direct.

A behavioral model for a direct class ASMI is illustrated in

Figure 3-7. In the model, an event is represented as a short

duration (much less than 1 µs) positive pulse that is associ-

ated with a given Enable/Event pair n. The Enable/Event

pair is represented by a pair of simple “D” flip/flops that can

be set (write 1 to Q) or cleared (write 0 to Q) by software.

The EN bit can be written high or low, but the FLAG bit can

only be cleared. By GeodeLink architecture convention,

writing a 1 to a FLAG bit clears it; writing a 0 has no effect.

If the EN bit is 1, then the 0-to-1 transition of the event

pulse clocks a 1 into the SMI FLAG flip/flop.

All of the ASMI bits are ORed together to form the GLD

ASMI. The GLD ASMI is routed through the GLIU where it

is ORed with all other device ASMIs to form the CS5535

ASMI.

Figure 3-7. Direct ASMI Behavioral Model

A behavioral model for a in-direct class ASMI is illustrated

in Figure 3-8 on page 69. An event is represented as

before, but it is first applied to some type of Native Event

kind that records multiple IRQ sources. Alternatively, there

might be multiple independent Native Event registers that

are at some point ORed together to form a single Native

Event Summary Signal (NESS). In general, a NESS can

also be an IRQ signal routed to the PIC subsystem. Hence,

depending on operational needs, a NESS can be an IRQ or

ASMI.

The important point is that the NESS 0-to-1 transition

clocks a 1 into the SMI FLAG flip/flop. The event only in-

directly causes the SMI FLAG bit to be set. Further note

that the Event[X] and ASMI[n+1] are independently clear-

able. ASMI[n+1] can be cleared, while leaving NESS at a 1

state.

After

such

clearing

action

with

NESS

high,

ASMI[n+1] will not set again. Alternatively, Event[X] could

be cleared without effecting the state of ASMI[n+1].

Lastly, it is possible to clear and set ASMI[n+1] while NESS

remains at a constant high state. Consider the following

sequence:

Assume EN[n] is high.

Event[X] occurs and NESS makes a 0-to-1 transition

that sets ASMI[n+1].

Software clears ASMI[n+1] by writing a 1 to it.

NESS remains high because Event[X] has not been

cleared.

EN[n] is cleared to 0.

EN[n] is set to a 1 and causes ASMI[n+1] to be set

again.

Note:

Step 5 could also be performed between steps 2

and 3 instead, yielding the same result. The

sequence of setting EN[n] to 0 followed by setting

EN[n] to 1 is called an Enable Toggle.

The previous sequence is used when multiple events X, Y,

Z, etc. all OR to form a single NESS. The events are shar-

ing a single NESS. Under this arrangement, the following

Virtual System Architecture (VSA) software sequence

would be typical:

Assume EN[n] is high.

Event[X] fires and causes a CS5535 ASMI.

VSA searches the GX2/CS5535 system looking for the

ASMI source and finds ASMI[n+1].

VSA clears EN[n] to 0 and begins to perform the

actions associated with Event[X].

While the “actions” are being taken, Event[Y] fires.

VSA

“actions”

include

clearing

Event[X]

and

ASMI[n+1].

NESS remains high because Event[Y] has fired.

SMI MSR

FLAG Bit[n+1]

ASMI

[n+1]

GLD ASMI

Clear_By_Software

Set_By_Software

Clear_By_Software

Event

[X]

Bit[n]

Other ASMI

FLAG Bits

CS5535 Datasheet(PDF) 68 Page - National Semiconductor (TI)

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