CS5535 datasheet(427/555 Pages) NSC

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RTC Register Descriptions (Continued)

5.15.2.10 Year (RTC_YEAR)

5.15.2.11 RTC Control Register A (RTC_CRA)

This register controls test selection among other functions. This register cannot be written before reading bit 7 of RTC_CRD

(VRT bit).

I/O Address

09h

Type

R/W

Reset Value

00h

RTC_YR Register Map

76543

210

YR_DATA

RTC_YR Bit Descriptions

Bit

Name

Description

7:0

YR_DATA

Year Data. This register holds the two least significant digits of a four-digit year. For

example, if the year is 2007, this register would contain the equivalent of ‘07’. Values

may be 00 to 99 in BCD format or 00 to 63 in binary format. Reset by VPP power-up.

I/O Address

0Ah

Type

R/W

Reset Value

20h

RTC_CRA Register Map

76543

210

UIP

DIV_CHN_CTL

PIR_SEL

RTC_CRA Bit Descriptions

Bit

Name

Description

UIP (RO)

Update in Progress (Read Only). This RO bit is not affected by reset. This bit reads 0

when bit 7 of RTC_CRB is 1.

0: Timing registers not updated within 244 µs.

1: Timing registers updated within 244 µs.

6:4

DIV_CHN_CTL

Divider Chain Control. These R/W bits control the configuration of the divider chain for

timing generation and register bank selection. They are cleared to 010 as long as bit 7

of RTC_CRD (VRT bit) is 0.

00x: Oscillator Disabled.

10x: Test.

010: Normal Operation.

11x: Divider Chain Reset.

011: Test.

3:0

PIR_SEL

Periodic Interrupt Rate Select: These R/W bits select one of fifteen output taps from

the clock divider chain to control the rate of the periodic interrupt. They are cleared to

000 as long as bit 7 of RTC_CRD (VRT bit) is 0.

0000:

No interrupts

1000:

3.906250 ms

0001:

3.906250 ms

1001:

7.812500 ms

0010:

7.812500 ms

1010:

15.625000 ms

0011:

0.122070 ms

1011:

31.250000 ms

0100:

0.244141 ms

1100:

62.500000 ms

0101:

0.488281 ms

1101:

125.000000 ms

0110:

0.976562 ms

1110:

250.000000 ms

0111:

1.953125 ms

1111:

500.000000 ms

CS5535 Datasheet(PDF) 427 Page - National Semiconductor (TI)

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