CS5535 datasheet(432/555 Pages) NSC

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5.16 GPIO SUBSYSTEM REGISTER DESCRIPTIONS

The registers for the General Purpose Input Output (GPIO)

are divided into two sets:

• Standard GeodeLink Device MSRs (Shared with DIVIL,

see Section 5.6.1 on page 299.)

• GPIO Native Registers

The MSRs are accessed via the RDMSR and WRMSR pro-

cessor instructions. The MSR address is derived from the

perspective of the CPU Core. See Section 3.2 "CS5535

MSR Addressing" on page 53 for more details on MSR

addressing.

The GPIO Native registers are accessed via a Base

Address Register, MSR_LBAR_GPIO (MSR 5140000Ch),

as I/O Offsets. (See Section 5.6.2.5 on page 310 for bit

descriptions of the Base Address Register.)

The Native registers associated with GPIO configuration

are broadly divided into three categories:

GPIO Low/High Bank Feature Bit Registers.

These registers (summarized in Table 5-57) control

basic GPIO features. The Feature Bit registers use the

atomic programming model except where noted. See

Section 5.16.1 "Atomic Bit Programming Model" on

page 436 for details.

Input Conditioning Function Registers.

These registers (summarized in Table 5-58 on page

434) are associated with the eight digital filter/event

counter pairs that can be shared with the 32 GPIOs.

These registers are not based on the atomic bit pro-

gramming model.

GPIO Interrupt and PME Mapper Registers.

These registers (summarized in Table 5-59 on page

435) are used for mapping any GPIO to one of the

eight PIC-level interrupts or to one of the eight PME

(Power Management Event) inputs.

The reference column in the summary tables point to the

page where the detailed register maps and bit descriptions

are listed. The Low Bank refers to GPIO[15:0] while the

High Bank refers to GPIO[31:16].

Note:

All register bits dealing with GPIO31, GPIO30,

GPIO29 and GPIO23 are reserved.

Table 5-57. GPIO Low/High Bank Feature Bit Registers Summary

GPIO I/O

Offset

Type

Width

(Bits)

Reset

Value

Reference

GPIO Low Bank Feature Bit Registers

00h

R/W

GPIO Low Bank Output Value (GPIOL_OUT_VAL)

FFFF0000h

Page 438

04h

R/W

GPIO Low Bank Output Enable (GPIOL_OUT_EN)

FFFF0000h

Page 438

08h

R/W

GPIO Low Bank Output Open-Drain Enable

(GPIOL_OUT_OD_EN)

FFFF0000h

Page 439

0Ch

R/W

GPIO Low Bank Output Invert Enable

(GPIOL_OUT_INVRT_EN)

FFFF0000h

Page 439

10h

R/W

GPIO Low Bank Output Auxiliary 1 Select

(GPIOL_OUT_AUX1_SEL)

FFFF0000h

Page 440

14h

R/W

GPIO Low Bank Output Auxiliary 2 Select

(GPIOL_OUT_AUX2_SEL)

FFFF0000h

Page 441

18h

R/W

GPIO Low Bank Pull-Up Enable (GPIOL_PU_EN)

1000EFFFh

Page 442

1Ch

R/W

GPIO Low Bank Pull-Down Enable (GPIOL_PD_EN)

EFFF1000h

Page 442

20h

R/W

GPIO Low Bank Input Enable (GPIOL_IN_EN)

FFFF0000h

Page 443

24h

R/W

GPIO Low Bank Input Invert Enable

(GPIOL_IN_INVRT_EN)

FFFF0000h

Page 443

28h

R/W

GPIO Low Bank Input Filter Enable

(GPIOL_IN_FLTR_EN)

FFFF0000h

Page 444

2Ch

R/W

GPIO Low Bank Input Event Count Enable

(GPIOL_IN_EVNTCNT_EN)

FFFF0000h

Page 445

30h

(Note 1)

GPIO Low Bank Read Back (GPIOL_READ_BACK)

00000000h

Page 450

34h

R/W

GPIO Low Bank Input Auxiliary 1 Select

(GPIOL_IN_AUX1_SEL)

FFFF0000h

Page 446

38h

R/W

GPIO Low Bank Events Enable (GPIOL_EVNT_EN)

FFFF0000h

Page 446

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