CS5535 datasheet(483/555 Pages) NSC

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PMC Register Descriptions (Continued)

5.18.2.5

PM Timer (PM_TMR)

PM_TMR is the data value register for the 32-bit timer running from the 3.579 MHz clock.

5.18.2.6

General Purpose Events Status 0 (PM_GPE0_STS)

PM_GPE0_STS is the Status register for General Purpose Events.

Status events are cleared by writing a 1 to the

appropriate FLAG bit. Writing 0 has no effect. By convention, bits [23:0] are associated with the Working domain while bits

[31:24] are associated with Standby domain. During Standby, bits [23:0] are unconditionally cleared. These events are all

individually enabled and then ORed together to form the System Control Interrupt (SCI).

PM2_CNT Bit Descriptions

Bit

Name

Description

15:8

RSVD

Reserved. ACPI defines this as an 8-bit register. It has been extended so that all PML

registers are at least 16 bits. Writes to these bits are a “don’t care”. Reads always

return 0.

7:1

RSVD

Reserved. By convention write 0, but other values are “don’t care”. Reads return 0

value.

0ARB_DIS

System Arbiter Disable. Disables when high. Reads return value written.

This bit is required by the ACPI specification, but internally is not connected to any PM

logic.

ACPI I/O Offset

10h

Type

Reset Value

00000000h

PM_TMR Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

TMR_VAL

PM_TMR Bit Descriptions

Bit

Name

Description

31:0

TMR_VAL (RO)

Timer Value (Read Only). This read only counter is driven by the 3.579545 MHz clock.

Writes are always a “don’t care”.

The counter runs continuously as long as the system is in the Working state; otherwise,

counting is stopped. It stops counting when SUSP# is asserted and starts counting

when SUSPA# has been de-asserted after having been asserted. The value in this reg-

ister is lost in the Standby state.

ACPI I/O Offset

18h

Type

R/W

Reset Value

00000000h

CS5535 Datasheet(PDF) 483 Page - National Semiconductor (TI)

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