LXP730 datasheet(21/70 Pages) INTEL

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Multi-Rate DSL Framer — LXP730

Datasheet

2.9.2

ADPLL Center Frequency: The computation of CFREQ

The center frequency of the ADPLL is set by an 18-bit unsigned fractional number, CFREQ(17:0).

This value is programmed in PLLCTL1, PLLCTL2, and PLLCTL3. CFREQ(17:0) is the ratio of

the Numerically Controlled Oscillator (NCO) and MCLK, and is shown below. The 218 is the

normalizing factor to express it in integer notation. It must then be converted to hexadecimal to

load into the CFREQ register.

The output of the NCO is divided by 2 before being provided to the clock multiplex circuitry and

the optional PROG_DIV block. This must be taken into account when deciding upon the frequency

for the NCO.

The NCO/MCLK ratio should be set to a value greater than or equal to 0.5 but less than 0.98. This

ensures that there will be the maximum number of bits of accuracy for the NCO to generate the

frequency. The ratio of 0.5 normalized with 2

18 is 131072 or in hexadecimal, 20000h. This is the

smallest recommended value.

Equation 1. Calculation of CFREQ

Table 4 list values for: CFREQ(17:0), Programmable Divider, and NCO frequency for a MCLK of

16.384MHz in several configurations.

2.10

Clock Generation and Distribution

The LXP730 has a flexible clock generation circuit as shown in Figure 3. The clocks for the PCM

and codec interfaces can be an independent external input, a division of MCLK, a division of the

ADPLL output, or the ADPLL output as selected by the PCM Configuration 1 register

(PCM_CFG1) and the Codec Configuration register (COD_CFG).

The PCM port is considered to be in slave mode when its clock source is the external pin. The PCM

frame pulse is also sourced from its external PFRM pin when the clock is configured as such. The

PCM port is in master mode for the other three settings. The PCM frame pulse is derived from the

internal PCLK and driven out on the PFRM pin.

The codec port initially has the CCLK pin tristated until it is configured as an output by setting the

CCLK_OE bit in the MISC_CTL register. It is never an input. The external source for the codec

clock is the PCLK pin. This allows simultaneous use of the PCM and codec interfaces with the

PCM bus providing the clock and allowing MCLK to be some other frequency that may not be

suitable to divide down for the codecs.

The ADPI clock is not derived from the circuit shown in Figure 3, but rather comes from the TSI

module. The TSI keeps track of opportunities to transmit bytes into the DSL frame and creates a

burst of eight pulses to clock a byte of data to insert in the MX direction. The TSI unloads data

from the DX DSL direction and also creates a burst of eight pulses to clock a byte of data to the

external device connected to the ADPI interface.

CFREQ

ROUND

NCOFREQ

()

MCLK

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LXP730 Datasheet(PDF) 21 Page - Intel Corporation

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