MCP3910 datasheet(4/90 Pages) MICROCHIP

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MCP3910

DS20005116D-page 4

 2012-2020 Microchip Technology Inc.

Gain Error

-6

—

Note 5

Gain Error Drift

—

ppm/°C

Integral Nonlinearity

INL

—

ppm

Measurement Error

—

0.1

—

Measured with a 10,000:1

dynamic range (from 600 mVPeak

to 60 µVPeak), AVDD= DVDD = 3V,

measurement points averaging

time: 20 seconds

Differential Input

Impedance

ZIN

232

—



G = 1, proportional to 1/AMCLK

142

—



G = 2, proportional to 1/AMCLK

—



G = 4, proportional to 1/AMCLK

—



G = 8, proportional to 1/AMCLK

—



G = 16, proportional to 1/AMCLK

—



G = 32, proportional to 1/AMCLK

Signal-to-Noise and

Distortion Ratio (Note 2)

SINAD

93.5

—

Total Harmonic Distortion

(Note 2)

THD

—

-107

-103

dBc

Includes the first 35 harmonics

Signal-to-Noise Ratio

(Note 2)

SNR

—

Spurious-Free Dynamic

Range (Note 2)

SFDR

—

112

—

dBFS

Crosstalk (50, 60 Hz)

CTALK

—

-122

—

AC Power Supply Rejection

AC PSRR

—

-73

—

AVDD =DVDD =3V + 0.6VPP,

50/60 Hz, 100/120 Hz

DC Power Supply Rejection

DC PSRR

—

-73

—

AVDD = DVDD = 2.7V to 3.6V

DCCommon-ModeRejection DC CMRR

—

-105

—

VCM from -1V to +1V

TABLE 1-1:

ANALOG SPECIFICATIONS (CONTINUED)

Electrical Specifications:

Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz;

PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER[1:0] = 11; BOOST[1:0] = 10, VCM =0V;

TA = -40°C to +125°C (Note 1); VIN =1.2 VPP = -0.5 dBFS @ 50/60 Hz on all channels.

Characteristic

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1:

All specifications are valid down to -45°C operation.

This specification implies that the ADC output is valid over this entire differential range and that there is no

distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum

signal range, VIN =1.2 VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and

Formulas”

for definition. This parameter is established by characterization and not 100% tested.

For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 00,

RESET[1:0] = 00, VREFEXT = 0, CLKEXT = 0.

For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 11,

VREFEXT = 1, CLKEXT = 1.

Applies to all gains. Offset and gain errors depend on PGA gain setting. See Section 2.0 “Typical

Performance Curves”

for typical performance.

Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied

continuously to the part with no damage.

For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum

frequency, defined in Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger

values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined

range in Table 5-2.

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