UPD75P068CU datasheet(21/42 Pages) RENESAS

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µPD75P068

Conditions

AC CHARACTERISTICS (Ta = -40 to +85

°C, VDD = 2.0 to 6.0 V)

Notes 1. The cycle time of the CPU clock (

Φ)

depends on the connected resonator

frequency, the system clock control

control register (PCC).

The figure on the right side shows the

cycle time tCY characteristics for the

supply voltage VDD during main sys-

tem clock operation.

2. This value becomes 2tCY or 128/fX

according to the setting of the inter-

rupt mode register (IM0).

Parameter

Symbol

tCY

fTI

tTIH,

tTIL

tINTH,

tINTL

tRSL

CPU clock cycle time

(minimum instruction

execution time = 1

machine cycle)Note 1

TI0 input frequency

TI0 input high/low

level width

Interrupt input high/

low level width

RESET low level width

Min.

Typ.

Max.

Unit

122

125

275

µs

MHz

kHz

µs

0.95

3.8

114

0.48

1.8

Note 2

VDD = 4.5 to 6.0 V

Operated by main

system clock

pulse

Operated by subsystem clock pulse

VDD = 4.5 to 6.0 V

INT0

INT1, INT2, and INT4

KR0 to KR3

0.5

Operation guaranteed

range

tCY vs VDD

(Main system clock in operation)

Power supply voltage VDD [V]

UPD75P068CU Datasheet(PDF) 21 Page - Renesas Technology Corp

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