UPD75P308 datasheet(21/36 Pages) RENESAS

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µPD75P308

AC CHARACTERISTICS (Ta = -10 to + 70

°C, VDD = 5V ±5%)

Operation Other Than Serial Transfer

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

w/main system clock

w/subsystem clock

INT0

KR0-7, INT1, 2, 4

tCY

fTI

tTIH, tTIL

tINTH,

tINTL

tRSL

CPU Clock Cycle Time*1

(Minimum Instruction

Execution Time

= 1 Machine Cycle)

TI0 Input Frequency

TI0 Input High-, Low-Level

Widths

Interrupt Input High-, Low-Level

Widths

RESET Low-Level Width

0.95

µs

114

122

125

µs

MHz

0.48

µs

0.5

(with main system clock)

Supply voltage V

[V]

vs V

* 1: The CPU clock (

Φ) cycle time is determined

by the oscillation frequency of the connected

oscillator, system clock control register

(SCC), and processor clock control register

(PCC).

The figure on the right is cycle time tCY vs.

supply voltage VDD characteristics at the

main system clock.

2: 2tCY or 128/fXX depending on the setting of

the interrupt mode register (IM0).

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