MP86957

– INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA

MP86957 Rev. 1.1

www.MonolithicPower.com

12

7/10/2020

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© 2020 MPS. All Rights Reserved.

APPLICATION INFORMATION

PWM

The PWM input pin is capable of tri-state input.

When the PWM input signal is within the tri-state

threshold window for 40ns (typical), THT or TLT,

the high-side MOSFET (HS-FET) turns off

immediately and the low-side MOSFET (LS-FET)

remains in diode emulation mode until zero

current detection. The tri-state PWM input can

be from a forced middle voltage PWM signal.

Alternately, the PWM input can be floated and

the internal current source will charge the signal

to a middle voltage. The PWM timing diagram

shows the propagation delay definition from

PWM to the SW node (see Figure 1).

Place a resistor divider (e.g. 1.2kΩ to VDD and

1kΩ to GND) at the PWM pin to anticipate when

the controller’s PWM tri-state enters Hi-Z (High

impedance) mode. This function prevents the

LS-FET from turning on if the TOUT/FLT signal

is pulled up after a fault occurs and the controller

responds the fault and shuts down by placing

PWM to HiZ mode. The PWM pin does not

require a resistor divider if the controller’s PWM

tri-state is at a middle voltage.

Diode Emulation Mode

In diode emulation mode, when PWM is at either

low or tri-state input, the LS-FET turns on

whenever the inductor current is positive. The

LS-FET is off if the inductor current is negative

or after it has crossed zero current. Diode

emulation mode can be enabled by:

1. Driving PWM to middle state

2. Floating the PWM pin

Current Sense

The IOUT pin is a bi-directional current source

proportional to the inductor current. The current

sensing gain is 5

μA/A, and a resistor is used to

program the voltage gain proportional to the

inductor current if needed.

The IOUT pin output has two states (see Table

1). In disable mode (EN = low), the current sense

circuit is disabled and IOUT is in Hi-Z (high-

impedance) state.

Table 1: IOUT Output States

PWM

EN

IOUT

PWM

High

Active

x

Low

Hi-Z

The IOUT pin voltage range of 0.7V to 2.1V is

required to get IOUT

’s accurate current output.

In general, there is a resistor (RIOUT) connected

from IOUT to an external voltage, which is

capable of sinking a small current to provide

enough voltage to meet the required operating

voltage range. Determine a proper reference

voltage (VCM) and/or RIOUT value using Equation

(1) and Equation (2):

IOUT

IOUT

CM

0.7V

I

R

V

2.1V









(1)

IOUT

SW

IOUT

I

I

G



(2)

Where VCM is a reference voltage connected to

RIOUT.

The Intelli-PhaseTM current sense output can be

used to accurately monitor the output current.

The cycle-by-cycle current information from

IOUT can be used for phase current balancing,

over-current

protection,

and

active

voltage

positioning (output voltage droop).

Positive and Negative Inductor Current Limit

When HS-FET over-current is detected, the HS-

FET on-pulse is truncated for that PWM cycle. If

an HS current limit event is detected for eight

consecutive cycles, the TOUT/FLT pin is pulled

high to VDD, during which time the driver

continues responding to PWM. Once four

consecutive

normal

cycles

are

detected,

TOUT/FLT is cleared.

When the LS-FET detects a -40A valley current,

the part turns off the LS-FET and turns on the

HS-FET for 200ns to limit the negative current.

The LS-FET negative current limit will not trigger

a fault report.

Over-Temperature Fault Flag

If the junction temperature rises above 145°C,

TOUT/FLT is pulled to VDD, during which time

the driver continues responding to PWM. Once

the junction temperature falls below 133°C, the

fault flag clears.