MP86957

– INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA

MP86957 Rev. 1.1

www.MonolithicPower.com

13

7/10/2020

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Low-Side Catastrophic Failure Protection

If the HS-FET VDS is greater than 0.7V when the

HS-FET is on, the low-side catastrophic failure

protection is triggered. The MP86957 stops

responding to PWM and latches, and TOUT/FLT

is pulled high immediately. After 200ns, the

PWM impedance becomes 10k to GND. The

MPS multiphase controller can detect this

impedance and record which phase experiences

this failure.

This fault latch can be released by toggling EN

or recycling VDD/VIN.

Temperature Sense Output with Fault

Indicator (TOUT/FLT)

TOUT/FLT

reports

junction

temperature.

It

sources a voltage proportional to the junction

temperature when VDD is higher than the UVLO

threshold. The gain is 8mV/°C, and the offset is

+800mV at 25°C. TOUT pins from multi-phase

topologies can be tied together to report the

highest TMON signals to the controller.

TOUT/FLT are pulled to VDD when a fault event

is detected. It reports three fault events: HS-FET

over-current limit, over-temperature, low-side

catastrophic failure.

For multiphase operation, connect TOUT/FLT of

each Intelli-PhaseTM together (see Figure 3).

L1

PWM

Intelli-

Phase

TM

PWM1

L2

PWM

VIN

VIN

PWM2

TOUT/FLT

VIN

VIN

TOUT/FLT

Intelli-

Phase

TM

VOUT

COUT

Multiphase

Controller

Temperature

ADC

Intelli-Phase

TM

Power Stage

Figure 3: Multiphase Temperature Sense

Utilization

PCB Layout Guidelines

PCB layout plays an important role in achieving

stable operation. For optimal performance, refer

to Figure 4 and follow the guidelines below:

1. Place the input MLCC capacitors as close to

VIN and PGND as possible. The major

MLCC capacitors should be placed on the

same layer as the MP86957.

2. Place

as

many

VIN

and

PGND

vias

underneath the package as possible, in-

between VIN or PGND long pads.

3. Place a VIN copper plane on the second

inner layer to form the PCB stacking in a +/-

/+ pattern to reduce the parasitic impedance

from the input MLCC cap to the MP86957.

The copper plane on inner layer must at least

cover the VIN vias underneath the package

and the input MLCC capacitors.

4. Place more PGND vias close to the PGND

pin/pad to minimize parasitic resistance and

impedance, as well as thermal resistance.

5. Place the BST and VDRV capacitors as

close to the device

’s pins as possible. Use a

≥20 mil width trace to route the path. Avoid

the via for the BST driving path. It is

recommended to use 0.1µF to 0.22µF for the

bootstrap capacitor.

6. Place the VDD decoupling capacitor close to

the device. Connect AGND and PGND at the

point

of

the

VDD

capacitor

’s ground

connection.

7. Keep the IOUT signal trace away from high-

current paths, such as SW and PWM.