UPD78P4908 datasheet(39/66 Pages) RENESAS

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µPD78P4908

Data Sheet U11681EJ2V0DS00

CLOCK OUTPUT OPERATION (TA = –40

°C to +85°C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

Remark n:

Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16)

tCYK (system clock cycle time)

OTHER OPERATIONS (TA = –40

°C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

Note

Use the RESET low-level width to ensure the lapse of the oscillation settling time when the power is applied.

Remark tCYSMP: Sampling clock set by software

tCYCPU: CPU operation clock set by software in the CPU

Unit

Parameter

CLKOUT cycle time

CLKOUT low-level width

CLKOUT high-level width

CLKOUT rise time

CLKOUT fall time

Symbol

tCYCL

tCLL

tCLH

tCLR

tCLF

MIN.

MAX.

32,000

Conditions

VDD = 4.5 to 5.5 V, 0.5T – 10

0.5T – 20

VDD = 4.5 to 5.5 V, 0.5T – 10

0.5T – 20

4.5 V

≤ VDD < 5.5 V

4.0 V

≤ VDD < 4.5 V

4.5 V

≤ VDD < 5.5 V

4.0 V

≤ VDD < 4.5 V

Unit

µs

Parameter

NMI low-level width

NMI high-level width

INTP0 low-level width

INTP0 high-level width

Low-level width for INTP1-

INTP3 and CI

High-level width for INTP1-

INTP3 and CI

Low-level width for INTP4 and

INTP5

High-level width for INTP4 and

INTP5

RESET low-level widthNote

RESET high-level width

Symbol

tWNIL

tWNIH

tWIT0L

tWIT0H

tWIT1L

tWIT1H

tWIT2L

tWIT2H

tWRSL

tWRSH

MIN.

4 tCYSMP

4 tCYCPU

MAX.

Conditions

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