AX88170L datasheet(7/39 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AX88170

PRELIMINARY

2.0 Signal Description

The following terms describe the AX88170 pin-out:

All pin names with the “/” suffix are asserted low.

The following abbreviations are used in following Tables.

Input

Pull Up

Output

Pull Down

I/O

Input/Output

Power Pin

Open Drain

2.1 USB Bus Interface Signals Group

SIGNAL

TYPE

PIN NO.

DESCRIPTION

D+

I/O

USB Data Plus Pin

D-

I/O

USB Data Minus Pin

Tab – 1 USB bus interface signals group

2.2 EEPROM Signals Group

SIGNAL

TYPE

PIN NO.

DESCRIPTION

EECS

EEPROM Chip Select : EEPROM chip select signal.

EECK

EEPROM Clock : Signal connected to EEPROM clock pin.

EEDI

EEPROM Data In : Signal connected to EEPROM data input pin.

EEDO

I/PU

EEPROM Data Out : Signal connected to EEPROM data output pin.

Tab – 2 EEPROM bus interface signals group

2.3a MII interface signals group (MAC mode)

When /S_RMII=1 and /S_MAC=0

SIGNAL

TYPE

PIN NO.

DESCRIPTION

RXD[3:0]

I/PU

29, 28

27, 26

Receive Data: RXD[3:0] is driven by the PHY synchronously with respect

to RX_CLK.

CRS

I/PD

Carrier Sense: Asynchronous signal CRS is asserted by the PHY when

either the transmit or receive medium is non-idle.

RX_DV

I/PD

Receive Data Valid: RX_DV is driven by the PHY synchronously with

respect to RX_CLK. Asserted high when valid data is present on RXD

[3:0].

RX_ER

I/PD

Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK, is

asserted for one or more RX_CLK periods to indicate to the port that an

error has detected.

RX_CLK

I/PU

Receive Clock: RX_CLK is a continuous clock that provides the timing

reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from

the PHY to the MII port of the MAC.

COL

I/PD

Collision: this signal is driven by PHY when collision is detected.

TX_EN

Transmit Enable: TX_EN is transition synchronously with respect to the

rising edge of TX_CLK. TX_EN indicates that the port is presenting

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