AX88170L datasheet(8/39 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AX88170

PRELIMINARY

SIGNAL

TYPE

PIN NO.

DESCRIPTION

nibbles on TXD [3:0] for transmission.

TXD[3:0]

21, 20

19, 18

Transmit Data: TXD[3:0] is transition synchronously with respect to the

rising edge of TX_CLK. For each TX_CLK period in which TX_EN is

asserted ,TXD[3:0] are accepted for transmission by the PHY.

TX_CLK

Transmit Clock: TX_CLK is a continuous clock from PHY. It provides the

timing reference for the transfer of the TX_EN and TXD[3:0] signals from

the MII port to the PHY.

MDC

Station Management Data Clock: The timing reference for MDIO. All data

transfers on MDIO are synchronized to the rising edge of this clock. MDC

is a 2.5MHz frequency clock output.

MDIO

I/O/PU

Station Management Data Input/Output: Serial data input/output transfers

from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII

specification.

Tab – 3 MII interface signals group (MAC mode)

2.3b MII interface signals group (PHY mode)

When /S_RMII=1 and /S_MAC=1

SIGNAL

TYPE

PIN NO.

DESCRIPTION

RXD[3:0]

29, 28

27, 26

Receive Data: Basically RXD[3:0] is transformed from TXD[3:0] of MAC

mode of MII interface.

CRS

Carrier Sense: Basically CRS is transformed from TX_EN of MAC mode of

MII interface.

RX_DV

Receive Data Valid: Basically RX_DV is transformed from TX_EN of MAC

mode of MII interface.

RX_ER

Receive Error: No used

RX_CLK

Receive Clock: Basically RX_CLK is sourced from internal 25MHz local

clock.

COL

Collision: this signal is generated by internal logic when collision is

detected.

TX_EN

I/PD

Transmit Enable: Basically TX_EN is simulation from RX_DV of MAC

mode of MII interface.

TXD[3:0]

I/PU

21, 20

19, 18

Transmit Data: Basically TXD[3:0] is simulation from RXD[3:0] of MAC

mode of MII interface.

TX_CLK

Transmit Clock: Basically TX_CLK is sourced from internal 25MHz local

clock.

Tab – 4 MII interface signals group (PHY mode)

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