UPD63335 datasheet(21/58 Pages) RENESAS

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Data Sheet S15003EJ6V0DS

µPD63335

1.6.9

Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:1:1:0

• CLKIOS = “0”: Input of both BIT_CLK and LRCLK

• CLKIOS = “1”: Output of both BIT_CLK and LRCLK

• BIT_CLK: 64 fS

• Data I/O occurs via the L channel while LRCLK is at high level and occurs via the R channel while LRCLK is at low

level.

• SI and SO have right-justified data input and output.

1.6.10 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:1:1:1

• CLKIOS = “0”: Input of both BIT_CLK and LRCLK

• CLKIOS = “1”: Output of both BIT_CLK and LRCLK

• BIT_CLK: 64 fS

• Data I/O occurs via the R channel while LRCLK is at high level and occurs via the L channel while LRCLK is at low

level.

• SI and SO have right-justified data input and output.

L15 L14 L13

R15 R14 R13

R2 R1 R0

Left channel data

Right channel data

Left channel data

Right channel data

LRCLK

BIT_CLK

64 fs

L15 L14 L13

R15 R14 R13

R2 R1 R0

L15 L14 L13

R15 R14 R13

R2 R1 R0

Left channel data

Right channel data

Left channel data

Right channel data

LRCLK

BIT_CLK

64 fs

L15 L14 L13

R15 R14 R13

R2 R1 R0

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