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UPD72042B Datasheet(PDF) 28 Page - Renesas Technology Corp |
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UPD72042B Datasheet(HTML) 28 Page - Renesas Technology Corp |
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28 / 92 page ![]() µPD72042B 26 Data Sheet S13990EJ3V0DS (3) Data write mode C/D SCK SIONote A0 A1 A2 A3 ×× × D0 D1 D2 D3 D4 D5 D6 D7 0 State Data write mode Control mode (selection of register write) Serial clock counter reset pointer Note SIO pin input state Caution Register overwrite is started immediately after the eighth clock rising edge. All registers other than TBF are overwritten at the eighth clock rising edge. (Data of less than eight clock periods is ignored.) |
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