APEX20K datasheet(37/117 Pages) ALTERA

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Implementing Logic in ROM

In addition to implementing logic with product terms, the ESB can

implement logic functions when it is programmed with a read-only

pattern during configuration, creating a large LUT. With LUTs,

combinatorial functions are implemented by looking up the results, rather

than by computing them. This implementation of combinatorial functions

can be faster than using algorithms implemented in general logic, a

performance advantage that is further enhanced by the fast access times of

ESBs. The large capacity of ESBs enables designers to implement complex

functions in one logic level without the routing delays associated with

linked LEs or distributed RAM blocks. Parameterized functions such as

LPM functions can take advantage of the ESB automatically. Further, the

Quartus II software can implement portions of a design with ESBs where

appropriate.

Programmable Speed/Power Control

APEX 20K ESBs offer a high-speed mode that supports very fast operation

on an ESB-by-ESB basis. When high speed is not required, this feature can

be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs

that run at low power incur a nominal timing delay adder. This

Turbo BitTM option is available for ESBs that implement product-term

logic or memory functions. An ESB that is not used will be powered down

so that it does not consume DC current.

Designers can program each ESB in the APEX 20K device for either

high-speed or low-power operation. As a result, speed-critical paths in the

design can run at high speed, while the remaining paths operate at

reduced power.

I/O Structure

The APEX 20K IOE contains a bidirectional I/O buffer and a register that

can be used either as an input register for external data requiring fast setup

times, or as an output register for data requiring fast clock-to-output

performance. IOEs can be used as input, output, or bidirectional pins. For

fast bidirectional I/O timing, LE registers using local routing can improve

setup times and OE timing. The Quartus II software Compiler uses the

programmable inversion option to invert signals from the row and column

interconnect automatically where appropriate. Because the APEX 20K IOE

offers one output enable per pin, the Quartus II software Compiler can

emulate open-drain operation efficiently.

The APEX 20K IOE includes programmable delays that can be activated to

ensure zero hold times, minimum clock-to-output times, input IOE

A path in which a pin directly drives a register may require the delay to

ensure zero hold time, whereas a path in which a pin drives a register

through combinatorial logic may not require the delay.

APEX20K Datasheet(PDF) 37 Page - Altera Corporation

APEX20K Datasheet(HTML) 37 Page - Altera Corporation

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