MLP2N06CL

http://onsemi.com

5

Figure 9. Thermal Response (MLP2N06CL)

t, TIME (s)

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

0.01

0.1

1.0

1.0E−05

1.0E−04

1.0E−03

1.0E−02

1.0E−01

1.0E+00

1.0E+01

D = 0.5

0.02

0.2

0.05

0.1

SINGLE PULSE

0.01

PULSE GENERATOR

50

W

z = 50

W

50

W

DUT

Figure 10. Switching Test Circuit

INVERTED

90%

90%

10%

10%

50%

90%

50%

PULSE WIDTH

Figure 11. Switching Waveforms

ACTIVE CLAMPING

SMARTDISCRETES technology can provide on−chip

realization of the popular gate−to−source and gate−to−drain

Zener diode clamp elements. Until recently, such features

have been implemented only with discrete components

which consume board space and add system cost. The

SMARTDISCRETES technology approach economically

melds these features and the power chip with only a slight

increase in chip area.

In practice, back−to−back diode elements are formed in a

polysilicon region monolithicly integrated with, but

electrically isolated from, the main device structure. Each

back−to−back diode element provides a temperature

compensated voltage element of about 7.2 V. As the

polysilicon region is formed on top of silicon dioxide, the

diode elements are free from direct interaction with the

conduction regions of the power device, thus eliminating

parasitic electrical effects while maintaining excellent

thermal coupling.

To achieve high gate−to−drain clamp voltages, several

voltage elements are strung together; the MLP2N06CL uses

8 such elements. Customarily, two voltage elements are used

to provide a 14.4 V gate−to−source voltage clamp. For the

MLP2N06CL, the integrated gate−to−source voltage

elements provide greater than 2.0 kV electrostatic voltage

protection.

The avalanche voltage of the gate−to−drain voltage clamp

is set less than that of the power MOSFET device. As soon

as the drain−to−source voltage exceeds this avalanche

voltage, the resulting gate−to−drain Zener current builds a

gate voltage across the gate−to−source impedance, turning

on the power device which then conducts the current. Since

virtually all of the current is carried by the power device, the

gate−to−drain voltage clamp element may be small in size.

This technique of establishing a temperature compensated

drain−to−source sustaining voltage (Figure 7) effectively

removes the possibility of drain−to−source avalanche in the

power device.

The gate−to−drain voltage clamp technique is particularly

useful for snubbing loads where the inductive energy would

otherwise avalanche the power device. An improvement in

ruggedness of at least four times has been observed when

inductive energy is dissipated in the gate−to−drain clamped

conduction mode rather than in the more stressful

gate−to−source avalanche mode.