AT83SND2CMP3B datasheet(120/241 Pages) ATMEL

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120

4341F–MP3–03/06

AT8xC51SND2C/MP3B

Table 16-2.

Priority Levels

16.11.2

USB Interrupt Control System

As shown in Figure 16-16, many events can produce a USB interrupt:

•

TXCMPL: Transmitted In Data (Table 1 on page 126). This bit is set by hardware when the

Host accept a In packet.

•

RXOUTB0: Received Out Data Bank 0 (Table 1 on page 126). This bit is set by hardware

when an Out packet is accepted by the endpoint and stored in bank 0.

•

RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 1 on page

126). This bit is set by hardware when an Out packet is accepted by the endpoint and stored

in bank 1.

•

RXSETUP: Received Setup (Table 1 on page 126). This bit is set by hardware when an

SETUP packet is accepted by the endpoint.

•

STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 1 on page 126).

This bit is set by hardware when a STALL handshake has been sent as requested by

STALLRQ, and is reset by hardware when a SETUP packet is received.

•

SOFINT: Start of Frame Interrupt (Table 16-5 on page 123). This bit is set by hardware when

a USB start of frame packet has been received.

•

WUPCPU: Wake-Up CPU Interrupt (Table 16-5 on page 123). This bit is set by hardware

when a USB resume is detected on the USB bus, after a SUSPEND state.

•

SPINT: Suspend Interrupt (Table 16-5 on page 123). This bit is set by hardware when a USB

suspend is detected on the USB bus.

IPHUSB

IPLUSB

USB Priority Level

0..................Lowest

3..................Highest

AT83SND2CMP3B Datasheet(PDF) 120 Page - ATMEL Corporation