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AT83SND2CMP3B Datasheet(PDF) 163 Page - ATMEL Corporation |
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AT83SND2CMP3B Datasheet(HTML) 163 Page - ATMEL Corporation |
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163 / 241 page ![]() 163 4341F–MP3–03/06 AT8xC51SND2C/MP3B Figure 19-10. Master SPI Interrupt Flows 19.3.6 Slave Mode with Polling Policy Figure 19-11 shows the initialization phase and the transfer phase flows using the polling. The transfer format depends on the master controller. SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of recep- tion” check). This provides the fastest effective transmission and is well adapted when communicating at high speed with other Microcontrollers. However, the process may then be interrupted at any time by higher priority tasks. SPI Initialization Interrupt Policy Enable interrupt ESPI =1 SPI Interrupt Service Routine Select Master Mode MSTR = 1 Select Bit Rate program SPR2:0 Select Format program CPOL & CPHA Enable SPI SPEN = 1 Read Status Read SPSTA Start New Transfer write data in SPDAT Last Transfer? Get Data Received read SPDAT Disable interrupt SPIE = 0 Select Slave Pn.x = L Start Transfer write data in SPDAT Deselect Slave Pn.x = H |
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