AT83SND2CMP3B datasheet(182/241 Pages) ATMEL

182 / 241 page

182

4341F–MP3–03/06

AT8xC51SND2C/MP3B

Figure 21-2. Complete Data Transfer on TWI Bus

The four operating modes are:

•

Master transmitter

•

Master receiver

•

Slave transmitter

•

Slave receiver

Data transfer in each mode of operation are shown in Figure 21-3 through Figure 21-6. These

figures contain the following abbreviations:

Acknowledge bit (low level at SDA)

Not acknowledge bit (high level on SDA)

Data

8-bit data Byte

START condition

STOP condition

Master Receive

Master Transmit

SLA

Slave Address

GCA

General Call Address (00h)

Read bit (high level at SDA)

Write bit (low level at SDA)

In Figure 21-3 through Figure 21-6, circles are used to indicate when the serial interrupt flag is

set. The numbers in the circles show the status code held in SSSTA. At these points, a service

routine must be executed to continue or complete the serial transfer. These service routines are

not critical since the serial transfer is suspended until the serial interrupt flag is cleared by

software.

When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the

appropriate service routine. For each status code, the required software action and details of the

following serial transfer are given in Table 21-2 through Table 21-6.

21.1.1

Bit Rate

The bit rate can be selected from seven predefined bit rates or from a programmable bit rate

generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 21-9). The

predefined bit rates are derived from the peripheral clock (FPER) issued from the Clock Controller

block as detailed in section "Oscillator", page 13, while bit rate generator is based on timer 1

overflow output.

Slave Address

SCL

SDA

MSB

R/W

direction

ACK

signal

Nth data Byte

ACK

signal

P/S

bit

from

receiver

from

receiver

Clock Line Held Low While Serial Interrupts Are Serviced

AT83SND2CMP3B Datasheet(PDF) 182 Page - ATMEL Corporation

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