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AT83SND2CMP3B Datasheet(PDF) 195 Page - ATMEL Corporation |
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AT83SND2CMP3B Datasheet(HTML) 195 Page - ATMEL Corporation |
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195 / 241 page ![]() 195 4341F–MP3–03/06 AT8xC51SND2C/MP3B 21.2 Registers Table 21-8. AUXCON Register AUXCON (S:90h) – Auxiliary Control Register Reset Value = 1111 1111b 76 5 4 3 2 1 0 SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0 Bit Number Bit Mnemonic Description 7SDA TWI Serial Data SDA is the bidirectional Two Wire data line. 6SCL TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. 5:1 Audio DAC Control Refer to Audio DAC interface section 0 KIN0 Keyboard Input Line |
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