ATMEGA64-16AI datasheet(19/393 Pages) ATMEL

19 / 393 page

ATmega64(L)

2490L–AVR–10/06

SRAM Data Memory

The ATmega64 supports two different configurations for the SRAM data memory as

listed in Table 1.

Figure 9 on page 20 shows how the ATmega64 SRAM Memory is organized.

The ATmega64 is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 locations reserved in the Opcode for the IN and OUT instructions.

For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the

ATmega64 is in the ATmega103 compatibility mode.

The first 4,352 data memory locations address both the Register File, the I/O memory,

Extended I/O memory, and the internal data SRAM. The first 32 locations address the

Extended I/O memory, and the next 4,096 locations address the internal data SRAM.

In ATmega103 compatibility mode, the first 4,096 data memory locations address both

the Register File, the I/O memory and the internal data SRAM. The first 32 locations

address the Register File, the next 64 location the standard I/O memory, and the next

4,000 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega64. This SRAM will

occupy an area in the remaining address locations in the 64K address space. This area

starts at the address following the internal SRAM. The Register File, I/O, Extended I/O

and internal SRAM occupy the lowest 4,352 bytes in Normal mode, and the lowest

4,096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so when

using 64KB (65,536 bytes) of External memory, 61,184 Bytes of External memory are

available in Normal mode, and 61,440 Bytes in ATmega103 compatibility mode. See

“External Memory Interface” on page 27 for details on how to take advantage of the

external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data

memory locations, the external data SRAM is accessed using the same instructions as

for the internal data memory access. When the internal data memories are accessed,

the read and write strobe pins (PG0 and PG1) are inactive during the whole access

cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR

Accessing external SRAM takes one additional clock cycle per byte compared to access

of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,

PUSH, and POP take one additional clock cycle. If the Stack is placed in external

SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the

2-byte Program Counter is pushed and popped, and external memory access does not

take advantage of the internal pipeline memory access. When external SRAM interface

is used with wait state, one-byte external access takes two, three, or four additional

clock cycles for one, two, and three wait states respectively. Interrupt, subroutine calls

and returns will need five, seven, or nine clock cycles more than specified in the AVR

Instruction Set manual for one, two, and three waitstates.

Table 1. Memory Configurations

Configuration

Internal SRAM

Data Memory

External SRAM

Data Memory

Normal mode

4096

up to 64K

ATmega103 compatibility mode

4000

up to 64K

ATMEGA64-16AI Datasheet(PDF) 19 Page - ATMEL Corporation

ATMEGA64-16AI Datasheet(HTML) 19 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL