ATMEGA64-16AI datasheet(29/393 Pages) ATMEL

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ATmega64(L)

2490L–AVR–10/06

before G low (t

su) must not exceed address valid to ALE low (tAVLLC) minus PCB wiring

delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

Pull-up and Bus Keeper

The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is

written to one. To reduce power consumption in sleep mode, it is recommended to dis-

able the pull-ups by writing the Port Register to zero before entering sleep.

The XMEM interface also provides a Bus Keeper on the AD7:0 lines. The Bus Keeper

can be disabled and enabled in software as described in “XMCRB – External Memory

Control Register B” on page 34. When enabled, the Bus Keeper will ensure a defined

logic level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated

by the XMEM interface.

Timing

External memory devices have different timing requirements. To meet these require-

ments, the ATmega64 XMEM interface provides four different wait states as shown in

Table 4. It is important to consider the timing specification of the external memory

device before selecting the wait-state. The most important parameters are the access

time for the external memory compared to the set-up requirement of the ATmega64.

The access time for the external memory is defined to be the time from receiving the

chip select/address until the data of this address actually is driven on the bus. The

access time cannot exceed the time from the ALE pulse is asserted low until data must

be stable during a read sequence (t

LLRL+ tRLRH - tDVRH in Table 137 to Table 144 on page

339). The different wait states are set up in software. As an additional feature, it is possi-

ble to divide the external memory space in two sectors with individual wait-state

settings. This makes it possible to connect two different memory devices with different

timing requirements to the same XMEM interface. For XMEM interface timing details,

please refer to Figure 159 to Figure 162, and Table 137 to Table 144.

Note that the XMEM interface is asynchronous and that the waveforms in the following

figures are related to the internal system clock. The skew between the internal and

external clock (XTAL1) is not guaranteed (varies between devices, temperature, and

supply voltage). Consequently the XMEM interface is not suited for synchronous

operation.

D[7:0]

A[7:0]

A[15:8]

SRAM

AD7:0

ALE

A15:8

AVR

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