PCA9421 datasheet(12/66 Pages) NXP

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NXP Semiconductors

PCA9421

Power management IC for low-power microcontroller applications

2. If there are output rails which may be enabled or disabled from initial mode setting to target mode setting,

then always make sure these rails which change from disabled to enabled take higher priority over rails

which change from enabled to disabled, i.e., make sure all the rails change from disabled status to enabled

status (reaches 90 % of its target value) first, and then start to disable these rails, changing from enable

status to disable status.

8.8 Mode selection by external pins (MODESEL0, MODESEL1)

Up on initial power-up, PCA9421 enters its default setting (Mode Setting 0). While operating under Mode Setting

0, by default the I2C register bit, EN_MODE_SEL_BY_PIN_0, is set to “0”, and the external signal applied on

the MODESEL0 and MODESEL1 pins are ignored. Only when the user sets EN_MODE_SEL_BY_PIN_0 to

“1”, can the mode control on the chip be programmed via MODESEL0 and MODESEL1 pin signal settings. The

MODESEL0 and MODESEL1 pins are not allowed to change while a mode change is in progress.

When EN_MODE_SEL_BY_PIN_x (x=0, 1, 2, or 3) bits are set to "1", MCU should satisfy the following

MODESEL signal conditions:

• No less than 5 µs pulse on each MODESEL signal.

• No more than 0.5 µs delay between MODESEL pins when transit from different modes.

In order to avoid impacting mode transition when there is disturbance in MODESELS pins

(EN_MODE_SEL_BY_PIN_x =1), it is proposed to implement one of the following designs:

• Hardware: Adding 10 nF capacitors to remove noise injection on MODESEL pins.

MODESEL1 pin voltage level

MODESEL0 pin voltage level

All Settings from

LOW (0)

Mode Setting 0

LOW (0)

HIGH (1)

Mode Setting 1

HIGH (1)

LOW (0)

Mode Setting 2

HIGH (1)

Mode Setting 3

Table 4. Mode selection by external pins (MODESEL0, MODESEL1)

8.9 SYSRSTn

The SYSRSTn is implemented as an open-drain output signal. It is used as an output of “power-good” indication

as well as to reset the microcontroller system.

The SYSRSTn signal is held from HIGH to LOW under one of following conditions:

1. When any of the enabled voltage rail output voltage drops below 90 % (typ) of its target value.

2. When any of the enabled voltage rail output voltage goes above 110 % (typ) of its target value

If any of the voltage rail is disabled by the user (by setting the corresponding enable bit in I2C register in each

mode setting, i.e., LDO1_EN_x, LDO2_EN_x, SW1_EN_x, SW2_EN_x), the SYSRSTn signal should NOT

assert (stays HIGH) under such scenario.

This also applies during the power-up/power-down sequence events, i.e., during power- up or power-down

event, the SYSRSTn signal should assert when any of the enabled rail has not reaches the 90 % to 110 % of its

target value. In other words, the SYSRSTn = 0 (LOW) needs to remain at such state until all enabled rails reach

90 % of the target values.

Once the condition that caused the SYSRSTn signal to go LOW is removed, then the SYSRSTn should refresh

accordingly.

Meanwhile, during the voltage change on-the-fly, this could be caused by:

PCA9421

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Product data sheet

Rev. 1.0 — 16 October 2023

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