SMSC DB – LPC47N227

Page 1

Rev. 03-29-07

PRODUCT PREVIEW

100 Pin Super I/O with LPC Interface for

Notebook Applications

FEATURES

3.3 Volt Operation (5V Tolerant)

PC99 and ACPI 1.0b Compliant

Programmable Wakeup Event Interface (nIO_PME

Pin)

SMI Support (nIO_SMI Pin)

GPIOs (29)

Two IRQ Input Pins

XNOR Chain

Intelligent Auto Power Management

2.88MB Super I/O Floppy Disk Controller

-

Licensed CMOS 765B Floppy Disk Controller

-

Software and Register Compatible with

SMSC's Proprietary 82077AA Compatible

Core

-

Supports One Floppy Drive Directly

-

Configurable Open Drain/Push-Pull Output

Drivers

-

Supports Vertical Recording Format

-

16-Byte Data FIFO

-

100% IBM Compatibility

-

Detects All Overrun and Underrun Conditions

-

Sophisticated Power Control Circuitry (PCC)

Including Multiple Powerdown Modes for

Reduced Power Consumption

-

DMA Enable Logic

-

Data Rate and Drive Control Registers

-

Swap Drives A and B

-

Non-Burst Mode DMA Option

-

48 Base I/O Address, 15 IRQ and 3 DMA

Options

-

Forceable Write Protect and Disk Change

Controls

Floppy Disk Available on Parallel Port Pins (ACPI

Compliant)

Enhanced Digital Data Separator

-

2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250

Kbps Data Rates

-

Programmable Precompensation Modes

Serial Ports

-

Two Full Function Serial Ports

-

High Speed NS16C550 Compatible UARTs

with Send/Receive 16-Byte FIFOs

-

Supports 230k and 460k Baud

-

Programmable Baud Rate Generator

-

Modem Control Circuitry

Infrared Communications Controller

-

IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer

IR Support

-

2 IR Ports

-

96 Base I/O Address, 15 IRQ Options and 3

DMA Options

Multi-Mode Parallel Port with ChiProtect

-

Standard Mode IBM PC/XT, PC/AT, and PS/2

Compatible Bidirectional Parallel Port

-

Enhanced Parallel Port (EPP) Compatible -

EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

-

IEEE 1284 Compliant Enhanced Capabilities

Port (ECP)

-

ChiProtect Circuitry for Protection Against

Damage Due to Printer Power-On

-

192 Base I/O Address, 15 IRQ and 3 DMA

Options

LPC Bus Host Interface

-

Multiplexed Command, Address and Data Bus

-

8-Bit I/O Transfers

-

8-Bit DMA Transfers

-

16-Bit Address Qualification

-

Serial IRQ Interface Compatible with

Serialized IRQ Support for PCI Systems

-

PCI nCLKRUN Support

-

Power Management Event (nIO_PME)

Interface Pin

100 Pin TQN, lead-free RoHS compliant package

and 100 Pin STQN, lead-free RoHS compliant

package

GENERAL DESCRIPTION

The SMSC LPC47N227 is a 3.3V PC 99 and ACPI 1.0b compliant Super I/O Controller.

The LPC47N227

implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the

ISA/X-bus with a substantial savings in pins used. The part also includes 29 GPIO pins.

The LPC47N227 incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16-

byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and

ECP support and one floppy direct drive support. The LPC47N227 does not require any external filter components, is

easy to use and offers lower system cost and reduced board area. The LPC47N227 is software and register

compatible with SMSC’s proprietary 82077AA core.

The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data

overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC’s patented data

LPC47N227