M41000000G datasheet(14/63 Pages) AMD

14 / 63 page

August 19, 2002

Am41DL6408G

P R E L I M INARY

Table 4.

Device Bus Operations—Flash Byte Mode, CIOf = V

IL; SRAM Byte Mode, CIOs = VSS

Legend: L = Logic Low = V

IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address

Input, Byte Mode, SADD = Flash Sector Address, A

IN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT =

Data Out, DNU = Do Not Use

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V

IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = V

ACC (9V), the program time will be reduced by 40%.

5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection”.

6. If WP#/ACC = V

IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and

Unprotection”. If WP#/ACC = V

HH, all sectors will be unprotected.

Word/Byte Configuration

The CIOf pin controls whether the device data I/O pins

operate in the byte or word configuration. If the CIOf

pin is set at logic ‘1’, the device is in word configura-

tion, DQ15–DQ0 are active and controlled by CE#f

and OE#.

If the CIOf pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ7–DQ0 are

active and controlled by CE#f and OE#. The data I/O

pins DQ14–DQ8 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE#f and OE# pins to V

IL. CE#f is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V

IH . T h e CI O f p i n de te r m i n es

whether the device outputs array data in words or

bytes.

Operation

(Notes 1, 2)

CE#f CE1#s CE2s OE# WE#

Addr.

LB#s

(Note 3)

UB#s

(Note 3)

RESET#

WP#/ACC

(Note 4)

DQ7–

DQ0

DQ15–

DQ8

Read from Flash

AIN

L/H

DOUT

High-Z

Write to Flash

(Note 3)

High-Z

Standby

CC ±

0.3 V

XXX

CC ±

0.3 V

High-Z

Output Disable

DNU

L/H

High-Z

Flash Hardware

Reset

L/H

High-Z

Sector Protect

(Note 5)

SADD,

A6 = L,

A1 = H,

A0 = L

VID

L/H

DIN

Sector Unprotect

(Note 5)

SADD,

A6 = L,

A1 = H,

A0 = L

(Note 6)

Temporary

Sector Unprotect

(Note 6)

High-Z

Read from SRAM

OUT

High-Z

Write to SRAM

High-Z

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