M41000000G datasheet(15/63 Pages) AMD

15 / 63 page

Am41DL6408G

August 19, 2002

P R E L I M INARY

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

Refer to the AC Flash Read-Only Operations table for

timing specifications and to Figure 14 for the timing di-

agram. I

CC1 in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE#f to V

IL, and OE# to VIH.

For program operations, the CIOf pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more in-

formation.

The device features an Unlock Bypass mode to facil-

itate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The

“Byte/Word Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 5 indicates the address

space that each sector occupies. Similarly, a “sector

address” is the address bits required to uniquely select

a sector. The “Command Definitions” section has de-

tails on erasing a sector or the entire chip, or suspend-

ing/resuming the erase operation.

The device address space is divided into four banks. A

“bank address” is the address bits required to uniquely

select a bank.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts V

HH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

HH from the WP#/ACC pin returns the device to nor-

mal operation. Note that V

HH must not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 20 for related in-

formation.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Sector/Sector Block Protection

and Unprotection and Autoselect Command Se-

quence sections for more information.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 21 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. I

CC6f and ICC7f in the table represent the cur-

rent specifications for read-while-program and

read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE#f and RESET# pins are both held at VCC ± 0.3 V.

(Note that this is a more restricted voltage range than

VIH.) If CE#f and RESET# are held at VIH, but not

within VCC ± 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The de-

vice requires standard access time (tCE) for read ac-

cess when the device is in either of these standby

modes, before it is ready to read data.

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