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P83C434CFP Datasheet(PDF) 17 Page - NXP Semiconductors |
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P83C434CFP Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 36 page ![]() 1997 Jul 03 17 Philips Semiconductors Product specification 8-bit microcontrollers with LCD-driver P83C434; P83C834 6.6.5 LCD CONTROL REGISTER (LCDCON) After an external or Power-on-reset the LCD Control Register holds the value 0CH (see Table 10) resulting in: • The LCD is disabled. All segment and backplane drivers are set to the VSS level. • BIAS is set to generate 1⁄3VDD(P). • Bits MD0 and MD1 reset the multiplex ratio to the 1 : 4 mode. Table 17 LCD Control Register (address B9H) Table 18 Description of LCDCON bits Table 19 Multiplex ratio mode selection 6.6.6 LCD SEGMENT DISPLAY REGISTERS (LCD0 TO LCD11) The 12 display registers, LCD0 to LCD11, are 8-bit derivative (Read/Write) registers which store LCD segment data. For detailed information, regarding the LCD0 to LCD11, see Table 23 in Section 6.7.7. 76543210 −−−− MD1 MD0 BIAS ENLCD BIT SYMBOL DESCRIPTION 7to4 − Reserved. 3 MD1 Mode bits. MD0 and MD1 determine the multiplex rate; see Table 19. 2 MD0 1 BIAS The BIAS bit sets the LCD voltage bias generator. If BIAS is: HIGH, then the LCD voltage bias generator is set to 1 ⁄2VDD(P). LOW, then the LCD voltage bias generator is set to 1 ⁄3VDD(P). 0 ENLCD Enable LCD. If ENLCD is: LOW, then the LCD is disabled. All segment and backplane drivers are set to the VSS level. HIGH, then the LCD is enabled and character display is possible. MD1 MD0 MULTIPLEX RATIO MODE 0 0 static 0 1 1:2 1 0 1:3 1 1 1:4 |
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