P89C738ABP datasheet(17/64 Pages) PHILIPS

17 / 64 page

1998 Apr 07

Philips Semiconductors

Product speciﬁcation

8-bit Flash microcontrollers

P89C738; P89C739

INTERRUPT SYSTEM

The P89C738 contains the same interrupt structure as the

PCB80C51BH, but with a six-source interrupt structure

with two priority levels (see Fig.10).

The external interrupts INT0 and INT1 can each be either

level-activated or transition-activated, depending on bits

IT0 and IT1 in SFR TCON. The flags that actually generate

these interrupts are bits IE0 and IE1 in TCON. When an

external interrupt is generated, the corresponding request

flag is cleared by the hardware when the service routine is

vectored to, only if the interrupt was transition-activated.

If the interrupt was level-activated the external source has

to hold the request active until the requested interrupt is

actually generated. Then it has to deactivate the request

before the interrupt service routine is completed, or else

another interrupt will be generated.

The Timer 0 and Timer 1 interrupts are generated by TF0

and TF1, which are set by a roll-over in their respective

timer/counter register (except for Timer 0 in Mode 3 of the

serial interface). When a timer interrupt is generated, the

flag that generated it is cleared by the on-chip hardware

when the service routine is vectored to.

The Serial Port interrupt is generated by the logical ‘OR’ of

RI and TI. Neither of these flags is cleared by hardware.

The service routine will normally have to determine

whether it was RI or TI that generated the interrupt, and the

bit will have to be cleared by software.

The Timer 2 interrupt is generated by the logical OR of TF2

and EXF2. Neither of these flags is cleared by hardware.

In fact the service routine may have to determine whether

it was TF2 or EXF2 that generated the interrupt, and the bit

will have to be cleared by software.

An additional (third) external interrupt is available, if

Timer 2 is not used as timer/counter or if Timer 2 is used

in the baud rate generator mode. That external interrupt 2

is falling-edge triggered. It shares the Timer 2 interrupt

vector, interrupt enable and interrupt priority bits. If bit

EXEN2 = 1 (T2CON.3), a HIGH-to-LOW transition at pin

P1.1/T2EX sets the interrupt request flag EXF2

(T2CON.6) and can be used to generate an external

interrupt.

The interrupt vectors are listed in Table 4.

Table 4

Interrupt vectors

SOURCE

PRIORITY

WITHIN LEVEL

VECTOR

ADDRESS

IE0

1 (highest)

0003H

TF0

000BH

IE1

0013H

TF1

001BH

RI + TI

0023H

TF2 + EXF2

6 (lowest)

002BH

Fig.10 P89C738/P89C739 interrupt sources.

handbook, halfpage

MGK193

IT1

INT1

TF1

TF0

TF2

EXF2

IE1

IT0

INT0

IE0

interrupt

sources

P89C738ABP Datasheet(PDF) 17 Page - NXP Semiconductors

P89C738ABP Datasheet(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL