©NEC Electronics Corporation 2004

78K0/KF2

ZUD-CC-04-0129-E

Data Published Oct 2004 N CP(K)

AC Characteristics

(1)Basic operation

(TA = -40 to +85

°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD =EVDD, VSS = EVSS = AVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.0 V

≤ VDD ≤5.5 V

0.1

16

µs

2.7 V

≤ VDD < 4.0 V

0.2

16

µs

High-speed

system

clock(fXH)

1.8 V

≤ VDD < 2.7 V

0.4

16

µs

2.7 V

≤ VDD < 5.5 V

0.25

4

µs

Main

system

clock(fXP)

operation

High-speed

Ring-OSC

clock(fRH)

1.8 V

≤ VDD < 2.7 V

0.5

4

µs

Instruction cycle (minimum

instruction execution time)

TCY

Subsystem clock(fSUB)operation

114

122

125

µs

4.0 V

≤ VDD ≤ 5.5 V

2.0

20.0

MHz

2.7 V

≤ VDD < 4.0 V

2.0

10.0

MHz

External main system clock

frequency

fEXCLK

1.8 V

≤ VDD < 2.7 V

2.0

5.0

MHz

External main system clock

input high-/low-level width

tEXCLKH,

tEXCLKL

(1/ fEXCLK

x 1/2) - 1

ns

External subsystem clock

frequency

fEXCLKS

32

32.768

35

kHz

External subsystem clock

input high-/low-level width

tEXCLKSH,

tEXCLKSL

(1/ fEXCLKS

x 1/2) - 5

ns

4.0 V

≤ VDD ≤ 5.5 V

2/fsam +

0.1

Note1

µs

TI000, TI010, TI001, TI011

input high-level width,

low-level width

tTIH0,

tTIL0

2.7 V

≤ VDD < 4.0 V

2/fsam +

0.2

Note1

µs

4.0 V

≤ VDD ≤ 5.5 V

10

MHz

2.7 V

≤ VDD < 4.0 V

10

MHz

TI50, TI51 input frequency

fTI5

1.8 V

≤ VDD < 2.7 V

5

MHz

4.0 V

≤ VDD ≤ 5.5 V

50

ns

2.7 V

≤ VDD < 4.0 V

50

ns

TI50, TI51 input high-level

width, low-level width

tTIH5,

tTIL5

1.8 V

≤ VDD < 2.7 V

100

ns

Interrupt input high-level

width, low-level width

tINTH,

tINTL

1

µs

Key return input low-level

width

tKR

250

ns

RESET low-level width

tRSL

10

Note2

µs

Notes 1. Selection of fsam = fPRS, fPRS /4, fPRS /256 or fPRS, fPRS /16, fPRS /64 is possible using bits 0 and 1

(PRM000,

PRM001

or

PRM010,PRM011)

of

prescaler

mode

register

00

and

01

(PRM00,PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock,

fsam = fPRS.

2. Input low level signal into RESET pin until power supply voltage is stabilized in the case of the

power supply voltage rise time is slowly (more than 3.4ms).