PDI1394P21 datasheet(4/28 Pages) PHILIPS

4 / 28 page

Philips Semiconductors

Objective specification

PDI1394P21

3-port physical layer interface

1999 Jul 09

Name

Description

I/O

Pin Numbers

Pin Type

C/LKON

CMOS 5V tol

I/O

Bus Manager Contender programming input and link-on output. On

hardware reset, this terminal is used to set the default value of the

contender status indicated during self-ID. Programming is done by tying

the terminal through a 10k

Ω resistor to a high (contender) or low (not

contender). The resistor allows the link-on output to override the input.

Following hardware reset, this terminal is the link-on output, which is

used to notify the LLC to power-up and become active. The link-on

output is a square-wave signal with a period of approximately 163 ns (8

SYSCLK cycles) when active. The link-on output is deasserted low when

the LPS input terminal is active.

DGND

Supply

3, 16, 20, 21, 28,

70, 80

—

Digital circuit ground terminals. These terminals should be tied together

to the low impedance circuit board ground plane.

D0–D7

CMOS 5V tol

7, 8, 10, 11, 12, 13,

14, 15

I/O

Data I/Os. These are bi-directional data signals between the

PDI1394P21 and the LLC. Bus holders are built into these terminals.

DVDD

Supply

6, 29, 30, 68, 69, 79

—

Digital circuit power terminals. A combination of high frequency

decoupling capacitors near each terminal are suggested, such as

paralleled 0.1

µF and 0.001 µF. Lower frequency 10 µF filtering

capacitors are also recommended. These supply terminals are

separated from PLLVDD and AVDD internal to the device to provide

noise isolation. They should be tied at a low impedance point on the

circuit board.

/ISO

CMOS

Link interface isolation control input. This terminal controls the operation

of output differentiation logic on the CTL and D terminals. If an optional

isolation barrier of the type described in Annex J of IEEE Std 1394–1395

is implemented between the PDI1394P21 and LLC, the /ISO terminal

should be tied low to enable the differentiation logic. If no isolation barrier

is implemented (direct connection), or bus holder isolation is

implemented, the /ISO terminal should be tied high to disable the

differentiation logic.

LPS

CMOS 5V tol

Link Power Status input. This terminal is used to monitor the power

status of the LLC, and is connected to either the VDD supplying the link

layer controller through a 1k

Ω resistor, or to a pulsed output which is

active when the LLC is powered. The pulsed output is useful when using

an isolation barrier. If this input is low for more than 25

ms, the LLC is

considered powered down. If this input is high for more than 20 ns, the

LLC is considered powered up. If the LLC is powered-down, the

PHY–LLC interface is disabled, and the PDI1394P21 performs only the

basic repeater functions required for network initialization and operation.

Bus holder is built into this terminal.

LREQ

CMOS 5V tol

LLC Request input. The LLC uses this input to initiate a service request

to the PDI1394P21. Bus holder is built into this terminal.

No Connect

9, 31, 71, 72

—

These pins are not internally connected, and consequently are “don’t

cares”. Other vendor’s pin compatible chips may require connections

and external circuitry on these pins.

PC0, PC1,

PC2

CMOS 5V tol

23, 24, 25

Power Class programming inputs. On hardware reset, these inputs set

the default value of the power class indicated during self-ID.

Programming is done by tying the terminals high or low. Refer to

Table 18 for encoding.

CMOS 5V tol

Power Down input. A logic high on this terminal turns off all internal

circuitry except the cable-active monitor circuits which control the CNA

output. Bus holder is built into this terminal. For more information, refer to

Section 17.3

PLLGND

Supply

74, 75

—

PLL circuit ground terminals. These terminals should be tied together to

the low impedance circuit board ground plane.

PLLVDD

Supply

—

PLL circuit power terminals. A combination of high frequency decoupling

capacitors near each terminal are suggested, such as paralleled 0.1

µF

and 0.001

µF. Lower frequency 10 µF filtering capacitors are also

recommended. These supply terminals are separated from DVDD and

AVDD internal to the device to provide noise isolation. They should be

tied at a low impedance point on the circuit board.

PDI1394P21 Datasheet(PDF) 4 Page - NXP Semiconductors

PDI1394P21 Datasheet(HTML) 4 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL